Verifying Antifuse NVM Hard Macro IP to Be Bulletproof


According to article in Design & Reuse from Cadence Design Systems entitled “The role of Verification IP in Complex core Design,” the author Saverio Fazzari, writes, “general studies suggest that on average 60 to 70 percent of development schedules are taken up with verification.” He calculates that, “in a hypothetical IC design case with a schedule of 1,000 man hours, 600 man hours, or 15 weeks, would be allocated to the verification task.” It is no wonder that third party IP verification needs to be bulletproof.

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