Integrating High Density Antifuse OTP NVM for Code Storage
July 2009 | Download PDF
Abstract
Semiconductor devices use non-volatile memory (NVM) to store its boot and firmware code. As SoC designs become more complex with added features, higher performance, and lower power, more semiconductor devices today use software to quickly adapt to market changes and enhance product differentiation. The adoption rate and size of the usage of NVM continue to grow. For code storage, the most common NVM technologies are ROM and external flash/EEPROM solutions. Following closely, antifuse one-time programmable (OTP) technology is becoming more popular for code storage, especially in the 90nm and below. Antifuse has unique advantages of using a standard CMOS process, being highly secure, field programmable, and having indefinite data retention. These traits drive down overall cost of the SOC product. As the process technology scales, it will favor antifuse since the OTP die area will scale, resulting in shorter programming time.
In this paper you will learn how antifuse NVM technology evolves with process scaling and its opportunities and challenges in high-density use.
Introduction
An antifuse NVM technology uses gate oxide breakdown as one-time programmable non-volatile memory. Gate oxide breakdown is achieved by applying a high voltage to the gate of a transistor while keeping a low voltage at the source side of the transistor. Before the breakdown, the area between the gate and the source of the transistor is isolated like a capacitor. After the breakdown, it behaves like a resistor. The advantage of the gate oxide breakdown technology is that the bit cell size is small, with only 2 transistors per bit cell. The programming can be done in wafer or packaged parts. Sensitive data stored using this technology is physically secure and has proven to be economically infeasible to break into. Gate oxide breakdown is applied with standard CMOS, and there is no additional cost associated with additional masks or processing steps.
Antifuse OTP NVM use is pervasive in many applications. At 1kbits or less, it can be used for trimming, yield enhancement, and Chip ID storage. At 8kb to 128kb, it can be used for secure code storage and ROM code patching. But at larger densities, it is less favorable for two reasons: 1) programming cost and 2) die cost.
Programming Cost
When the OTP is embedded into an SoC, it is programmed in an ATE tester. Comparing to overall BOM cost, antifuse OTP testing cost would be significantly higher at large densities. At 1Mb in 180nm, the programming cost with 0.5 code density is about $0.10. It’s even more expensive with mobile applications, as it uses an RF tester and cost may be 2x to 3x greater.
Die Cost
Die cost of 1Mb in 180nm is $0.04 to $0.08. For applications with small die size, it can contribute to 30-50% of the area cost.
But when migrating to deep submicron, these two constraints are eliminated.
Evolution of Antifuse NVM – 128Kb to 16Mb
Antifuse OTP memory evolves with technology scaling and gains benefits with smaller geometries. Unlike floating-gate, NVM technologies are limited in their ability to store charge because as the logic oxides get thinner, direct tunneling occurs, and the charge drains through the tunnel. Flash charge-storage technologies have scaling limitations around 80 to 85 Angstroms for the tunnel oxide thickness.
For antifuse NVM, as shown in figure 1, as the technology scales, the bitcell scales with core transistor design rules. In addition, as oxide thickness decreases, the programming voltage and the time to break the oxide decrease as well. Comparing to 180nm, the programming time improves by 10x in 40nm, and the programming voltage is reduced from 8.5V to 5.0V. With lower programming voltage, the area for peripheral logic is also reduced.
Figure 1: bitcell Scaling Trend
Figure 2: Programming Voltage versus Gate Oxide Thickness
Achieving High Yield at Large Density
As memory density increases, the memory core is increasingly prone to defects. The same is seen with other types of memory such as SRAMs. At high density, error correction is recommended, especially when the programming is done in-system. Programming failure in the field will cause an entire system to be discarded.
One form of error correction commonly used in memories to improve memory yield is redundancy. Because an antifuse OTP bitcell is so small, it can easily implement 100% redundancy to achieve high yield. For more size optimization of the memory module design, sector redundancy can be used to provide higher area-efficiency. Multi-row and column redundancy shown in Figure 3 can be implemented to achieve an optimal result of yield improvement vs. area trade off.
Figure 3: Optimal row and column redundancy to achieve max yield
Another form of error correction is ECC (error correction code) using a Hamming block code to overcome yield issues. Error correction has a lower bitcell overhead but may have performance impacts.
Achieving High Data Rate for Execution-in-place
Antifuse NVM is also able to achieve high data rate for execute-in-place (XIP) code storage. With XIP, programs are directly executed from the memory that is used to store the code. This eliminates the need for the shadow SRAM and increases overall system performance.
Some flash vendors develop fast serial flash solutions with multi-bit I/Os to support execute-in-place. SST’s Serial Quad I/O™ (SQI™) flash, for example, has a 4-bit multiplexed I/O serial interface and operates at a frequency reaching 100MHz. It provides a sustained data rate of up to 400Mb/s.
Comparing to external solutions, embedded solutions can easily bring up its data rate without sacrificing power and area due to I/O pin count increase. With a 2x access time improvement and a wider data bus, antifuse NVM can achieve a 4x to 16x improvement in bandwidth vs. SPI-based serial flash.
In addition, it can also provide faster random access time, as it does not need initialization cycles for the first read access. Typically, serial flash will need 40 cycles for the first byte data access.
Figure 4: Bandwidth Comparison
NVM Cost Comparison for Large Density Use
Several NVM solutions have been implemented today for code storage. Each NVM solution has its own advantage to accommodate the needs of the different market and application requirements. The density requirements for code storage are usually 512kb and above. For such densities, ROM and serial flash/EEPROM are the two most cost-effective solutions.
ROM is the most available and common solution. It is developed in 0.6um and below. However, at advanced processes, the re-spin cost and turnaround time (TAT) creates limitations when customers want to do code revisions. The competitive landscape of the IC industry has changed. Today, many customers are seeking the uniqueness and differentiation of their products through software optimization. Often software revisions are updated to add new features, improve system performance and adapt to market change. The time and cost for code revision through mask layer re-spin is difficult to justify.
The serial flash market has grown rapidly since its inception in 1997. It is able to drive down its cost with small geometry manufacturing and offers multiple-time programming capability. Designers can easily change their code without incurring any additional cost. Comparing to embedded NVM solutions, it has some disadvantages. It requires extra board space, and its ability to achieve high performance is limited by I/O numbers, off-chip power consumption and latency. Flash-based solutions are also less reliable and not secure due their floating-gate structure.
Figure 5 below illustrates the cost trend of using NVM technologies at 512kb density with 3 code revisions. For large density storage and few time code revision requirements, antifuse NVM cost reduces as technologies migrate to deep submicron, while ROM cost increases due to higher mask cost for re-spins. Comparing to serial flash as shown in Figure 6, antifuse NVM provides a cost comparable solution at 4Mb and below. This provides a good alternative for customers who are designing for small form-factor and low power applications.
Additionally, a new and exciting cost-saving feature of antifuse NVM allows customers to easily convert their OTP to a ROM with only one mask layer change. Once a customer’s product is mature, and the OTP content is fixed, customers using large density OTP in high volume production can leverage the OTP to ROM conversion to save on testing cost.
Figure 5: NVM cost comparison for 512kb density with 3 code revisions
Figure 6: Antifuse NVM cost in 45nm versus serial flash solution
Conclusion
Antifuse OTP NVM development moves forward with technology migration. It is not limited by technology scaling. With small geometries, its bitcell and programming time improves and allows SoC designers to put more OTP into their chip. High density antifuse OTP addresses the need for fast code revision, small form factor and execution in place (XIP) to store code.
Kilopass was the first to pioneer antifuse OTP in a standard CMOS process with no additional processing steps. Its patented 2T bitcells are implemented using standard core devices and follow DFM design rules. Today, Kilopass offers antifuse OTP NVM products from 180nm to 45nm with densities up to 1Mb. In deep submicron, Kilopass continues to build high density NVM products with its patented antifuse technology. Through design optimization and technology innovation, antifuse NVM technology is expected to expand its usage and penetrate into more applications.