A Comparison of Embedded Non-Volatile Memory Technologies and Their Applications
May 2009 | Download PDF
By Linh Hong, VP of Marketing and Applications at Kilopass Technology
Abstract
Abstract: With complexity of SOCs growing and time to market cycles shortening, designers need to have an arsenal of tricks to deliver highly differentiated products to market quickly. The arsenal may include SystemC, EDA tools to achieve a faster timing closure, and IP from high speed I/Os to memories. The most pervasive memory IPs are SRAM and ROM. Less pervasive memory IPs include non-volatile memory (NVM) technologies such as embedded Flash, electrical fuses, multi-time programmable (MTP) NVM, and one-time programmable (OTP) NVM. Though these embedded NVM technologies are not as main stream as their ROM sibling, they are gaining in popularity due to various added benefits including cost reduction, improved performance, enabling secure storage, and configurability. In this paper you will learn about all the embedded NVM technologies and the applications that benefit most from using embedded NVM.
Comparison of Embedded Non-Volatile Memory Technologies and Their Applications
In the logic NVM space, there are several technologies available in the market. They include:
- Embedded Flash solutions either use a split-gate architecture or a float-gate architecture depending on area, power, and performance requirements;
- Via or diffusion ROM create “1”s and “0”s through a double metal via or a change in Vt behavior from the implant in the diffusion;
- Electrical fuse solutions blow the silicide on the poly line creating a change in resistance is; these eFuses are typically provided by the foundry;
- Floating gate or charge trapping solutions use hot carrier injection as the programming mechanism;
- Antifuse solutions create “1”s from a hard oxide breakdown of the gate causing a resistive change.
Embedded Flash is used for code storage that changes often. It is common in microcontrollers (MCU) to provide flexibility to end applications to program any configurable code with one product. For example, MCU vendor A may sell a low end 8-bit MCU to a dozen washing machine makers. MCU vendor A only needs to develop one product to fit the needs of the washing machine makers. The washing machine makers can configure the code per each make and model. It is the most expensive of the embedded NVM technologies, but the most flexible. Both the vendor and the customer benefit from the flexibility to control inventory and provide differentiation.
ROM is used for code storage that is fixed. Often, this is code that does not change very often such as audio recording of “Happy Birthday” in a musical greeting card or fonts in an ink jet printer. It is the least expensive of the embedded NVM technologies but also the least flexible; programming of the ROM is done in fabrication. Once the IC is fabricated, the content cannot change without spinning mask layers.
Unlike ROM, the other standard CMOS technologies, electrical fuses, floating gate, and antifuse, can be programmed post fabrication. One pervasive use of these technologies is to recover parametric yield loss due to process variation or design marginality. For example, Ethernet requires +/- 100 ppm clock frequency accuracy which may not be achieved with silicon design unless there is fine tuning during ATE test. Likewise, Ethernet has a DAC that needs calibration for the target voltage range. The calibrated values for the DAC or the trim values for the clock can be stored in these NVM technologies.
1. 0 Embedded NVM Technologies
Cell structure, logic process compatibility, bit cell and macro areas, endurance, security, scalability, standby and active current, random access time, manufacturing backend turnaround time (TAT) and voltage/temperature tolerance are benchmarked in the Figure 1 below for all the embedded NVM technologies in the market.
| Embedded Flash | ROM | Electrical Fuse (OTP) | CMOS Floating Gate (MTP) | CMOS Floating Gate (OTP) | CMOS Antifuse (OTP) | |
|---|---|---|---|---|---|---|
| Cell Structure | Floating Gate 1T/2T | Masked 1T | Poly Fuse | Floating Gate 1T/2T | Floating Gate 1T/2T | Antifuse 1T/2T |
| Standard CMOS Compatible | No | Yes | Yes | Yes | Yes | Yes |
| Bitcell Area (Normalized) | 3 | <1 | 300 | 20 | 10 | 1 |
| 128Kb Area in 65nm (Normalized) | N/A | .5 | 8 | 24 | N/A | 1 |
| Endurance | 100-1000K | No | No | 10K | <5 | <5 |
| Standby & Active Current | Med | Low | High | Med | Med | Low |
| Random Access Time | Med | Fast | Slow | Med | Med | Fast |
| Security | Med | Low | Low | Med | Med | High |
| Scalability | Med(up to 90nm) | High | High | Med | Low (mainstream up to 180nm) | High |
| Additional Steps | +10 Mask | None | None | Wafer Bake | UV Erase, Wafer Bake | None |
| Manufacturing Backend TAT | None | +30 days to respin | None | None | None | None |
| High/Low Temperature & Voltage Tolerance | Low | High | Med | Low | Low | High |
Figure 1: Embedded NVM Benchmark
1.1 Electrical Fuse
Electrical fuse (eFuse) technology is a one-time programmable memory that is programmed by forcing a high current density through a conductor link to completely rupture it or make its resistance significantly higher.
Traditional eFuses as shown in Figure 2 are made of polysilicon or metals and are programmed by rupturing the conductor links. In addition to strict requirements for surrounding passivation and metals, these Fuses had unacceptable reliability because debris and shards can cause healing over time.
Figure 2: Poly/Metal Fuse
Modern eFuse is built on polysilicon with Cobalt or Nickel silicide on top. The fuse is programmed by a well-known reliability mechanism called electromigration in which electron momentum pushes the silicide atoms out of the conductor link. Still, most fuses can only be programmed at wafer and have stringent power requirements for programming. It makes programming in packaged parts difficult. The bitcell is the largest of the standard CMOS NVM technologies. For higher bit density memory applications, e.g. greater than 4Kb, the size of the fuse quickly begins to take up the area of the SOC. eFuse is usually custom-designed and provided by the foundry as macros. As a result, it cannot be legally ported to another foundry without the consent of the foundry.
1.2 CMOS Floating Gate
One of the most widely used cell types is the stacked-gate 1T cell which is a MOS transistor with one floating gate and one contacted gate overlapping each other, shown in Figure 3. The floating gate is completely insulated by a high quality oxide both at the bottom and top. A cell is typically programmed by channel hot electron (CHE) injection from the drain of the transistor and erased by Fowler-Nordheim (FN) electron tunneling through the bottom tunnel oxide. The presence or absence of charges (electrons or holes) in the floating gate determines if the transistor is on or off during read operations. Thus, a “1” or “0” is detected according to the channel conductance of the cell transistor. The advantages of floating gate devices is it can be erased and electrically programmed multiple times, up to 100K times.
Figure 3: Floating Gate Device
There are also other floating-gate devices such as double-poly 1.5T split gate and 2T cells. However, they all require additional masks and processing steps on top of the standard CMOS logic process. That adds manufacturing cost and makes high performance CMOS devices much more difficult to deliver. CMOS processes with embedded Flash are therefore at least 3 generations behind the most advanced logic process. MTPs that are truly CMOS compatible use at least 2 single poly transistors with gate oxide available for IO devices. For gate oxide less than 70A (3.3V IO), both program/erase endurance and data retention become unacceptable. Therefore, lack of migration path below 0.13um is a severe limitation for this kind of embedded NVMs. Foundry porting is also a formidable challenge because memory performance and reliability are very sensitive to minor differences in junction doping profiles, side-wall oxidation, spacer composition, back-end of line (BEOL) dielectrics.
1.3 Antifuse
An antifuse is the opposite of an eFuse. The circuit is open (high resistance) to begin with and is programmed closed by applying electrical stress that creates a low resistance conductive path. Antifuse NVM has been implemented for many decades using additional processing steps. Kilopass was the first to pioneer antifuse in a standard CMOS process with no additional processing steps. Kilopass holds patents for several flavors of bitcells, including the 1T and 2T.
A hard gate oxide breakdown is used as the one-time programmable non-volatile memory mechanism. The breakdown is achieved by applying a high voltage on the program gate (WLP) shown in Figure 4. Before the breakdown, between the gate and the source of the program transistor, it is isolated like a capacitor. After the breakdown, it behaves like a resistor between the gate and the source. The program transistor is isolated from the select transistor (WLR). Both the program and read transistors are implemented using core devices so as the technology scales, the bitcell scales.
Figure 4: Antifuse bitcell — 2T
The 1T bitcell, often called the split gate bitcell, is shown in Figure 5. The programming mechanism is the same, but the program and select transistors are combined into one. It becomes a new device structure. The 1T bitcell, if implemented in standard CMOS, will be larger than the 2T structure because the thick gate device (aka I/O device) uses an OD2 mask, non-critical low resolution. Given the OD2 layer is low grade, minimum geometry rules cannot be utilized. As a result, the bitcell will be larger than the 2T.
Figure 5: Antifuse bitcell — 1T (Modified CMOS Transistor)
The advantages of 2T include:
- DFM design rules are followed
- No extra requirements for both lithography and metrology
- Channel width and length of both the select and antifuse transistor are well controlled by active and poly CD alone
- Gate oxide reliability is no different from standard MOSFETs.
- Uniform breakdown under the entire gate, the current distribution is predictable and Gaussian
In the 1T solution, one word line is shared by the antifuse and select transistor resulting in area saving in decoder logic. Though the breakdown is in the thin oxide channel region, several factors are compromised to achieve this. The thin oxide area is determined by the triple overlay of active, OD2, and poly. The interface between thin and thick oxide is defect prone. Likewise, the select transistor channel length cannot be well controlled by standard fabrication tools, i.e., it is sensitive to CD control and OD2 alignment to the OD. To ensure high yield, a special mask step may be required for alignment or very tight process control.
Given the potential added cost of a special mask layer and the yield loss due to defects at the thin gate/thick gate interface, the 2T bitcell is the more reliable and cost effective. Kilopass offers NVM IP from 0.18 um to 40 nm using the 2T bitcell. Many of the designs up to 65 nm are ramping up to high volume production or have been in high volume production since 2003.
Kilopass offers three product families of OTP: XPM, SnapXPM, and BriteXPM. These products are available in over 30 foundry processes. With this expansive offering and comprehensive qualification methodology, Kilopass enables SOC designers to integrate embedded NVM from 180nm to 40nm.
2.0 Applications
For code that is fixed, ROM is the best embedded NVM technology. For code that changes very frequently, embedded Flash is the best embedded NVM technology. In between, there are valued applications where standard CMOS NVM fills a need. To determine which solution is best for your application, you have to review the tradeoffs (Figure 1) between each technology. For example, if it is a high volume product that will utilize a 2nd source foundry, the eFuse solution should not be chosen. You cannot legally port a foundry solution without consent. To minimize design re-work, it would be beneficial to look for a foundry agnostic solution.
Pervasive uses of embedded NVM technologies are in Figure 6.
| NVM Technology | Pervasive Market | Density | Application | Key Usage | Benefit |
|---|---|---|---|---|---|
| Embedded Flash | MCU | 64Kb-8Mb | Code Storage | Program code, Boot Code/Firmware |
|
| ROM | Greeting cards, toys, electronic Dictionaries | 4Kb-1Mb | Code Storage | Boot Code/Firmware |
|
| eFuse | Analog and Mixed Signal Ics, Consumer SOCs | 256bit-4Kb | Manufacturing & Usability, configuration | Trim and Calibration, IDs |
|
| Logic NVM Floating Gate (OTP) | Analog and Mixed Signal ICs | 1Kb-16Kb | Manufacturing & Usability, Configuration | Trim and Calibration, IDs |
|
| Logic NVM Floating Gate (MTP) | Analog and Mixed Signal ICs | 1Kb-16Kb | Manufacturing & Usability, Configuration | Trim and Calibration, IDs |
|
| Antifuse | Conditional Access, DTCP, HDCP, ePayment, Mobile Phone | 16bit-8Kb | Security | Chip ID, Encryption Key, Anti-piracy Codes, Certifications, IMEI/DRM |
|
| RF/Analog IC, CMOS Image Sensor, MEMS, Audio, LCD Display, RFID, embedded SOC, Mobile Handset Chipsets | 16bit-64Kb | Manufacturing & Usability, configuration | Trim & Calibration, Pixel Repair |
|
|
| MCU, Fixed and Wireless Broadband (RF, Wi-Fi, WiMax, LTE, etc.), Set-top Box, DTV, DVD | 128Kb-4Mb | Code Storage | Boot Code/Firmware Storage, Patch ROM Code |
|
Figure 6: Embedded NVM Applications
3.0 Conclusion
There are five embedded NVM technologies in the market: embedded Flash, ROM, eFuse, CMOS floating gate, and Antifuse. One benefit of the wide offering of technologies is that SOC designers and managers can choose the best solution for their end application. When choosing between the different technologies, an SOC designer or manager needs to consider the usage for the applications and the tradeoffs between each embedded NVM solution. Each has its advantages and disadvantages. For code that changes very frequently, SOC designers can only decide between MTP solutions such as embedded Flash and CMOS floating gate. For code that may change very infrequently and requires field programmability, OTP solutions are viable. Though Antifuse is an OTP, it can emulate an MTP for a few cycles of endurance. If 128Kb of code may need to be updated up to 8 times in the field, a 1Mb memory can be used.
Author Bio
Linh Hong is the Director of Marketing at Kilopass. She has been in the semiconductor industry for 13 years, mainly focused in broadband communication ASICs, high speed SERDES IP, and logic NVM IP. She has a breadth of experience including digital and mixed signal designs, technical marketing, field applications, and reliability engineering from Sun Microsystems and LSI Logic. She holds a BS in Physics and MSEE from University of California, Davis.