White Papers

SIDE-CHANNEL ATTACKS: How Differential Power Analysis (DPA) and Simple Power Analysis (SPA) Works

February 2017 | Read White Paper |

There are many techniques available for hackers to gain access to a system and obtain secret keys or other proprietary information– from invasive methods, such as microprobing, to noninvasive methods, such as cryptoanalysis. However, one of the easiest and most effective ways to extract the contents of a chip is through a side-channel attack using power analysis.

 

Reduced Memory Power for Internet of Things Applications

July 2016 | Read White Paper |

Memory has historically been a very stable technology, whether volatile or non-volatile. Incremental change happens constantly to improve performance, but it’s unusual for a major change to take place. The non-volatile one-time-programmable memory approach that Kilopass uses has been in place for thirteen years with no major changes. Now, however, Kilopass is readying a new memory array for the Gusto-3 family that takes advantage of the new X2Bit bitcell, and we view this as a significant event.

 

Kilopass’ X2Bit bitcell: OTP Dynamic Power Cut by Factor of 10

November 2015 | Read White Paper |

Kilopass’ X2Bit™ bitcell has achieved a breakthrough that allows it to reduce its dynamic current by a factor of 10, dropping from 100 µA/MHz to 10 µA/MHz. This paper first motivates in more detail why this is important and then illustrates the area where the change was made as well as the implications of that change.

 

A Comparison of Embedded Non-Volatile Memory Technologies and Their Applications

April 2015 | Read White Paper |

There are five embedded NVM technologies in the market: embedded Flash, ROM, eFuse, CMOS floating gate, and Antifuse. One benefit of the wide offering of technologies is that SOC designers and managers can choose the best solution for their end application. When choosing between the different technologies, an SOC designer or manager needs to consider the usage for the applications and the tradeoffs between each embedded NVM solution. Each has its advantages and disadvantages.

 

Vertical Crosspoint Memory Supports Ultra-Low-Power Devices for Internet of Things

December 2012 | Download PDF

With its widely varied smart devices, the Internet of Things (IoT) is creating a demand for microcontrollers made application specific by software instead of dedicated system on chip (SoC) designs. Warren East, CEO of ARM Ltd,1 said in an EE Times interview during ARM TechCon, “the Internet of Things for us is about the sale of microcontrollers. We think it is likely to follow a similar path to mobile phones.” The ARM CEO estimated that 8 billion MCUs shipped per year across all applications. Last year 15 percent of MCU shipments were based on the ARM architecture. With MCUs, one silicon device can address a wide range of applications simply by changing the program code, thus reducing the design cycle time and cost to build an SoC for individual market opportunities.

Yet another reason for MCUs instead of SoCs in IoT applications is government agency certification. In the EE Times’ MCU Designline, article, “MCUs: High-end devices flourish,”2 Editor Colin Holland, wrote, “electronics are proliferating in safety-critical applications and designers need simplified system certification and development. Sectors being looked at include industrial, medical, automotive, mil/aero and solar energy.” This argues for a common CPU and operating system not only to eliminate a SoC design cycle but also to shorten the regulatory review process.

This renewed interest in building microcontroller devices to power the devices comprising the IoT has shed a critical eye on the memory architecture that will be used to contain the program code of these devices. The three alternatives currently being used include read-only memory (ROM), embedded flash, and a combination of an external serial EEPROM and on-chip shadow SRAM. The Serial EEPROM provides the design permanent program storage during sleep or when power is removed while the shadow SRAM provides the memory that the CPU uses to execute the microcontroller’s program..

 

Using Non-Volatile Memory IP for Program Storage in System on Chip Designs

December 2012 | Download PDF

Using an intelligent tag/sensor as a typical embedded system, the attributes of the design are (1) finite feature set, (2) very high volume, (3) security, and (4) low power. In many instances these requirements will dictate a system-on-chip (SoC) design containing a CPU core with the program code stored on-board or in external EEPROM. The rationale for erasable memory is the need for frequent software updating during development, design retargeting or customization from stock prior to shipment and limited bug fixes or enhancements after the product is shipped into the field. The benefits of being able to change the code an unlimited number of times are appealing. However, in many if not all instances, the code is not changed frequently enough, if at all, to warrant unlimited programmability, nor is it wise to burden development costs onto the volume product. Low cost requirement is making embedded flash and EEPROM economically undesirable.

 

Kilopass Brings Gusto to Memory

June 2010 | Download PDF

Now designers have another option. Kilopass, already an established player in nonvolatile memory (NVM), has introduced an improved version of its antifuse OTP. Called Gusto, it’s licensed as process-portable intellectual property (IP). It is the industry’s first 4Mb OTP, quadrupling the capacity of existing OTP memories. It’s large enough to store boot code and system firmware, rather than just code patches, configuration code, and trim settings for analog components. In addition, Kilopass claims Gusto reads memory two to four times faster, cuts active power consumption by an order of magnitude, and slashes current leakage in standby mode by a factor of 40.

 

Integrating High Density Antifuse OTP NVM for Code Storage

July 2009 | Download PDF

For code storage, the most common NVM technologies used today are ROM and external flash/EEPROM solutions; however, in the 90nm and below, antifuse one-time programmable (OTP) technology is starting to gain in popularity. Antifuse has unique advantages of using a standard CMOS process, being highly secure, field programmable, and having indefinite data retention. These traits drive down overall cost of the SOC product. As the process technology scales, it will favor antifuse since the OTP die area will scale, resulting in shorter programming time.

 

Eliminating Embedded Non-Volatile Memory IP Risks in SOCs

March 2009 | Download PDF

With many embedded logic NVM options available, chip developers, foundry IP managers, and reliability managers need to narrow down the list of vendors by evaluating the risk of integrating an NVM IP. In this paper you will learn what to look for to ensure that the NVM IP will not cause headaches when your product goes into volume production.

 

Three Application Segments Require On-Chip OTP

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The use of high density one-time programmable (OTP) memory is now gaining considerable interest within the chip design community. The main reason for this renewed interest in OTP is the ability to tightly integrate high density permanent memory with digital logic in vanilla CMOS. The opportunity to tightly integrate OTP with SoC architectures sparks the system architect or designer’s imagination in three strong value-added application segments. They are: Security, SoC Configurability, and Manufacturability-Usability.

 

Profitable SoC Design: Using Logic NVM to Reduce SoC Costs

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Current trends in the semiconductor industry emphasize the inherent business and engineering risks associated with the development and production of a new chip. With very low incremental costs for implementing personalization design elements into system architectures,designers and technology leaders are now realizing tremendous value.

 

Methods for Configurable Hardware Design

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While adding post silicon production configurability has ample precedence with the introduction of FPGA devices in the late 1980’s, it is a more recent trend with SoC ASSP and ASIC architectures. As logic gates continue to get cheaper, the corresponding benefits of making devices configurable with the advantages of time-to-market, reduced project schedule risk, and inventory risk in post production are too important to ignore.

 

Secure, Low-cost On-Chip Code Storage for Embedded Signal-Processing Systems

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Consumer demand for appliances such as PDAs, digital cameras, cell phones, and MP3 players is forcing developers of such systems to continuously add new functionality to their products while offering them at lower price points. In addition, product vendors have become increasingly aware of and concerned about theft of product IP represented as code stored in silicon in these appliances. These market forces are changing the way such systems need to be designed.