Kilopass is the first to demonstrate its 2T antifuse non-volatile memory (NVM) technology is reliable in FinFET processes. Designers of complex SoC’s needing FinFET processes to deliver superior levels of scalability while achieving lower supply voltages than planar transistors have Kilopass’ embedded NVM available for their designs to enable differentiation through personalization, security and code storage. Kilopass has solutions available today at TSMC 16FF+ to engage.

Kilopass OTP Cell Architecture for FinFET-2T Cell with Stacked Two Standard NMOS

Kilopass’ new enablement for anti-fuse OTP NVM IP in FinFET, a 2T cell that consists of two standard core NMOS transistors. The cell array follows foundry defined constant CPP and conforms with DFM rule. Kilopass FinFET solution offers a choice of 1-Fin or 2-Fin cells without much area penalty.

OTP Cell Architecture for FinFET – 1T is not an option

  • IO gate length is limited to <250nm for gate patterning control
  • Define and control CDs inside a 250nm slot and over Fin topologies is not feasible, very sensitive to misalignments
  • IO transistors often require much more than 2 Fins
  • 1T will have a doped S/D region at the thin gate oxide side for FinFET processes where Fins are defined by SIT

Kilopass 2T OTP Cell and its Logic NMOS Device Dependency

2T = Two Standard NMOSFETs

  • Baseline Vt option
  • Lwp < Lwr for 28nm and above
  • Lwp = Lwr for 20nm and below
  • Conforms with DFM design rules

Device Sensitivity

  • Works for all logic process options
  • Cell design and OTP performance do depend on process architecture and control

Demonstrated Working Silicon on 16nm FinFET

Good programmed cell current across different cell designs

  • 16Kb cell array with varied cell architecture
  • Cell architecture consists of number of fins, transistor VT (LVT/SVT) and geometry (16 to 20nm)
  • Tight cell current distribution after programming demonstrated on several cell designs