Patents
Standard CMOS Antifuse NVM Patents
Kilopass has 57 patents issued or pending. Divided into three groups of fundamental bit cells – 1T, 2T, and 3.5T, Kilopass’ issued patents enable the embedding of OTP macros in standard CMOS products.
- 40 are issued, 14 pending in United States,China, Taiwan, Japan, and EPC.
- 21 Issued in United States for 1T, 2T, and 3.5T antifuse bitcell technologies.
- 5 for 1T, 15 for 2T, and 1 for 3.5T
| No. | Title | Patent Number | Issued Date | Category |
|---|---|---|---|---|
| 1 | Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric | US 6,667,902 | 12/23/2003 | 2T |
| 2 | Programming methods and circuits for semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric | US 6,671,040 | 12/30/2003 | 2T |
| 3 | Reprogrammable non-volatile memory using a breakdown phenomena in an ultra-thin dielectric | US 6,700.151 | 3/2/2004 | 2T |
| 4 | Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric | TW 198223 | 7/9/2004 | 2T |
| 5 | Smart card having memory using a breakdown phenomena in an ultra-thin dielectric | US 6,766,960 | 7/27/2004 | 2T |
| 6 | High density semiconductor memory cell and memory array using a single transistor | US 6,777,757 | 8/17/2004 | 1T |
| 7 | Reprogrammable non-volatile memory using a breakdown phenomena in an ultra-thin dielectric | TW 201454 | 9/3/2004 | 2T |
| 8 | Method of testing the thin oxide of a semiconductor memory cell that uses breakdown voltage | US 6,791,891 | 9/14/2004 | 2T |
| 9 | Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric | US 6,798,693 | 9/28/2004 | 2T |
| 10 | Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric | US 6,822,888 | 11/23/2004 | 2T |
| 11 | Reprogrammable non-volatile memory using a breakdown phenomena in an ultra-thin dielectric | CN Ser.No. 01129152.4 | 1/26/2005 | 2T |
| 12 | High density semiconductor memory cell and memory array using a single transistor | US 6,856,540 | 2/15/2005 | 1T |
| 13 | Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric | CN 01129151.6 | 2/23/2005 | 2T |
| 14 | High density semiconductor memory cell and memory array using a single transistor and buried n+ channel connection | US 6,898,116 | 5/24/2005 | 1T |
| 15 | Method of testing the thin oxide of a semiconductor memory cell that uses breakdown voltage | TW 234162 | 6/11/2005 | 2T |
| 16 | Smart card having memory using a breakdown phenomena in an ultra-thin dielectric | TW 234785 | 6/21/2005 | 2T |
| 17 | High density semiconductor memory cell and memory array using a single transistor and having variable gate oxide breakdown | US 6,940,751 | 9/6/2005 | 1T |
| 18 | Reprogrammable non-volatile memory using a breakdown phenomena in an ultra-thin dielectric | US 6,956,258 | 10/18/2005 | 2T |
| 19 | High density semiconductor memory unit and memory array using single transistor | CN Ser. No 03117374.8 | 11/30/2005 | 1T |
| 20 | High density semiconductor memory cell and memory array using a single transistor and having counter-doped poly and buried diffusion wordline | US 6,992,925 | 1/31/2006 | 1T |
| 21 | Methods and circuits for testing programmability of a semiconductor memory cell and memory array using a breakdown phenomenon in an ultra-thin dielectric | US 7,031,209 | 4/18/2006 | 2T |
| 22 | Methods and circuits for programming of a semiconductor memory cell and memory array using a breakdown phenomenon in an ultra-thin dielectric | US 7,042,772 | 5/9/2006 | 2T |
| 23 | Smart card having memory using a breakdown phenomena in an ultra-thin dielectric | CN Ser.No. 0112915.8 | 6/14/2006 | 2T |
| 24 | High density semiconductor memory cell and memory array using a single transistor | TW I261918 | 9/12/2006 | 1T |
| 25 | Programming methods and circuits for semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric | CN Ser.No. 03117372.1 | 1/31/2007 | 2T |
| 26 | 3.5 transistor non-volatile memory cell using gate breakdown phenomena | US 7,173,851 | 2/6/2007 | 3.5T |
| 27 | Memory transistor gate oxide stress release and improved reliability | US 7,269,047 | 9/11/2007 | 2T |
| 28 | 3.5-transistor non-volatile memory cell using gate breakdown phenomena | GB 1,777,708 (EPC) | 5/28/2008 | 3.5T |
| 29 | 3.5-transistor non-volatile memory cell using gate breakdown phenomena | FR 1,777,708 (EPC) | 5/28/2008 | 3.5T |
| 30 | 3.5 transistor non-volatile memory cell using gate breakdown phenomena | EP 1,777,708 (EPC) | 5/28/2008 | 3.5T |
| 31 | 3.5-transistor non-volatile memory cell using gate breakdown phenomena | DE 1,777,708 (EPC) | 5/28/2008 | 3.5T |
| 32 | Memory transistor gate oxide stress release and improved reliability | US 7,471,541 | 12/30/2008 | 2T |
| 33 | Non-volatile semiconductor memory based on enhanced gate oxide breakdown | US 7,471,540 | 12/30/2008 | 2T |
| 34 | Electrically programmable fuse bit | US Ser.No. 11/699,916 | Pending | Fuse |
| 35 | Non-volatile semiconductor memory based on enhanced gate oxide breakdown | Ser.No. 12/330,465 (Allowed) | Pending | 2T |
| 36 | Method and apparatus for programming auto shut off | Ser.No. 12/202,048 | Pending | 2T |
| 37 | Circuit for driving multiple charge pumps | Ser.No. 12/202,064 | Pending | 2T |
| 38 | Reduced bit line leakage current in non-volatile memories | US 7,586,787 | 9/8/2009 | 2T |
| 39 | Electrically programmable fuse bit | KR 38484.8018 | Pending | Fuse |
| 40 | Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric | JP Ser.No. 2003-529475 | Pending | 2T |
| 41 | Reprogrammable non-volatile memory using a breakdown phenomena in an ultra-thin dielectric | JP Ser.No. 2003-560928 | Pending | 2T |
| 42 | High density semiconductor memory cell and memory array using a single transistor | JP Ser.No. 2004-517521 | 11/20/2009 | 1T |
| 43 | Electrically programmable fuse bit | JP 38484.8018 | Pending | Fuse |
| 44 | 3.5 transistor non-volatile memory cell using gate breakdown phenomena | JP Ser.No. 2006-102753 | Pending | 3.5T |
| 45 | Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric | EP Ser.No. 02759714.5 | Pending | 2T |
| 46 | Reprogrammable non-volatile memory using a breakdown phenomena in an ultra-thin dielectric | EP Ser.No. 02804107.7 | Pending | 2T |
| 47 | High density semiconductor memory cell and memory array using a single transistor | EP Ser.No. 03751752.1 | Pending | 1T |
| 48 | Electrically programmable fuse bit | EP 38484.801 | Pending | Fuse |
| 49 | Semiconductor memory cell, memory array and method for operating the same | ZL03809184.4 (CN Ser.No. 03809184.4) | 8/5/2009 | 1T |
| 50 | Method of testing the thin oxide of a semiconductor memory cell that uses breakdown voltage | CN Ser.No. 200310110823.1 | 7/22/2009 | 2T |
| 51 | Methods and circuits for programming of a semiconductor memory cell and memory array using a breakdown phenomenon in an ultra-thin dielectric | CN Ser.No. 20051005387.X | Pending | 2T |
| 52 | High density semiconductor memory cell and memory array using a single transistor and having counter-doped poly and buried diffusion wordline | ZL200510052717.1 CN Ser.No. 200510052717.1 | 6/10/2009 | 1T |
| 53 | Electrically programmable fuse bit | CN 38484.8018 | Pending | Fuse |
| 54 | 3.5 transistor non-volatile memory cell using gate breakdown phenomena | CN Ser.No. 200610142513.1 | Pending | 3.5T |
| 55 | 3.5 transistor non-volatile memory cell using gate breakdown phenomena | TW Ser.No. 095108467 | Yes | 3.5T |
| 56 | One-Time Programmable Memory | US 12/802,206 | Pending | 2T |
| 57 | One-time programmable memory and method for making the same | US 12/819,566 | Pending | 1T |