2T Bitcell

The 2T CMOS antifuse bitcell consists of two core NMOS transistors. There is a program transistor (WLP) coupled in series with a select transistor (WLR).  When a normal supply voltage such as an I/O or core voltage is applied to the gates of the bitcell, no current is sensed along the bitline. The equivalent circuit for the program transistor is a capacitor. Since there is no current that flows along the bitline, the bitcell is “0” by default. When a large programming voltage is applied along the gate of the program transistor, a hard gate oxide breakdown occurs. A resistive path is created. The equivalent circuit for the program transistor becomes a resistor.  Current flowed along the bitline and a “1” is sensed. The “1”s can be programmed at any time. Once it is programmed, it cannot be reverted back to a “0”.

2T bitcell - before and after programming
2T Bitcell Cross Section
Since gate oxide breakdown is statistical in nature. It can break at the channel, halo, or LDD regions.  It is not important where it breaks but that the breakdown is uniform underneath the entire gate. From 180nm to 16nm, cell current distributions are Gaussian after programming. The width of the current distribution has no impact on the 2T product performance and reliability.

Graph showing typical 2T cell distribution


Antifuse NVM: Reliability, compatibility, and manufacturability

  1. Manufacturability for mass production and yield
    • No additional overlay tolerance or process control required
    • Standard NMOS transistor, not a new transistor
    • Follows DFM design rules
    • No Additional wafer processing operations
      • No wafer bake
      • No UV erase
  2. Reliability the same as foundry’s process
    • Standard CMOS baseline logic process technology
    • Exclusive use of standard Vt NMOS devices as supplied from the foundry