Itera™ Embedded MTP NVM
Itera™ Product Availability
- Capacity: 32b - 1Mb
- Process: 65nm - 40nm
- Foundries: TSMC, IBM, UMC
Itera™ is the industry’s first CMOS logic embedded multi-time programmable (MTP) non-volatile memory (NVM) in 40nm. It provides up to 1024 cycles of re-programmable storage. Itera is built using Kilopass’ patented 2T antifuse bitcell, which has been integrated in over 2 billion integrated circuits (ICs) as a solution for one-time programmable (OTP) NVM. The patented 2T bitcell has proven security critical for secure code storage applications. Itera contributes to enabling SoC designers a “Boundless Freedom to Embed.”
Using Itera, system-on-chip (SoC) designers can achieve significantly lower costs, higher performance, and improved integration by replacing external serial EEPROM and NOR flash in high-volume mobile and consumer applications. SoC designs that currently require external MTP NVM to store code or configuration data that change over the life of the product can now integrate Itera on chip to boost performance and reduce bill-of-material (BoM) costs and space of the final design. Itera enables a typical design to achieve an 24X increase in performance over Serial Peripheral Interface (SPI) flash and realize a cost savings of up to $6.3 million for a chip that achieves in a 10-million unit per year run rate.
Itera is available in MTP capacity from 32 bit to 1Mb and is now available at all major pure play foundries including TSMC, GLOBALFOUNDRIES, and UMC in 40nm bulk silicon with 65nm and 55nm in H2’11.
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Features
- Multi-time programmable synchronous memory
- Configurable options
* 32bit to 1Mb Itera memory
* External VPP programming plus field programmability features with internal charge pump
* Open Core Protocol (OCP) 3.0 Data bus interface - Program: x32
- Read: x32
- VDD (core supply)
- VDDIO (2.5V)
* Asymmetric power domain shut down - Data throughput: 20ns
- Programming Operating Temperature Range:
* -20C to 125C (Junction) - Read Operating Temperature Range:
* -40C to 125C (Junction) - SEC-DEC error correction scheme
- BIST to simplify manufacturing test
- Data Retention: more than 10 years
- Deliverables
* Front-end: LEF, Verilog model, Synopsys models
* Back-end: GDS, FRAM, CDL, PIPO log, DRC & LVS reports
* Collateral: datasheet, test methodology guide, integration guide, application notes