Embedded DRAM Provides Larger, Lower-Power Cache in Portable System SoCs

March 28th, 2013 by Kilopass Technology

Wei Zhang SM

In today’s portable system design, the memory architecture typically relies on flash as the main program store for a four-core symmetric multiprocessor compute engine. Between the processors and the flash is a small amount of SRAM to provide a high-speed cache for the processors.  The performance bottleneck for this system design is the SRAM cache. The silicon footprint of the SRAM cache limits the capacity available for a given desired die size. The leakage current of the cache impacts battery life and gets worse at successively smaller process geometries. What’s needed is a novel new memory bit cell that provides SRAM performance but overcomes these drawbacks.  Wei Zhang and his colleagues Ki Chul Chun and Chris H. Kim from the University of Minnesota have developed just such a bit cell based on the gain cell embedded DRAM (eDRAM) concept.  Fabricated in a standard 65nm logic process, the gain cell shows great promise.

The new gain cell was described in the Custom Integrated Circuits Conference (CICC), paper “A Write-Back-Free 2T1D Embedded DRAM with Local Voltage Sensing and a Dual-Row-Access Low Power Mode,” presented September 2012.  It is a different architecture compared to conventional eDRAMs that employ a capacitor to hold a binary 1 or a 6T SRAM that stores the data bit in a flip-flop.   Instead of a specialized capacitor to store information, the gain cell uses the native capacitance of two transistors A and B. The source of transistor A is wired to the gate of transistor B to form the storage bit cell.  Within the memory array transistor A connects between the write bit line and write word line and transistor B between the read bit line and read word line. A data bit is stored in the capacitance provided by the two transistors and any parasitics.

This elegant design provides benefits that make the gain cell an ideal candidate to replace SRAM in the processor architecture used in portable system design:  silicon footprint, power, and process scaling.  The cell size of the new gain cell is 43% smaller than that of a 6T SRAM in a 65nm CMOS process.  The immediate benefit is to roughly double the size of the processor cache.  The second advantage of the gain cell is power. The chips in portable designs are implemented in a silicon foundry’s lowest power process to achieve maximum playtime for the user. Bulk CMOS leakage increasing with each smaller process geometry is well documented.  SRAM power consumption is directly related to the amount of leakage current for each given process node and even in sleep mode, the memory continues to leak.  With the gain cell, there is no leakage associated with maintaining the charge, no constant leakage between Vdd and ground.  The only time power is needed is during memory refresh.

Because the gain cell is implemented in standard logic CMOS, it scales just as easily as SRAM but unlike SRAM it does not tax the power budget of the overall chip design in the same way. At smaller process nodes SRAM leakage rises. The gain cell’s power consumption during refresh remains relatively unchanged from one process node to the next since any increase in the refresh frequency is offset by the decrease in the switching capacitance and supply voltage.  Furthermore, because the gain cell needs no storage capacitor it scales far easier than the conventional 1T plus capacitor eDRAM that require multiple additional mask layers to produce the storage capacitor.  In scanning electron microscope views of 1TC eDRAM, the single transistor bit cell is dwarfed by the tall adjacent capacitor that must grow with each smaller process to contain sufficient charge to represent a data bit.

The other advantage that SRAM cache held over conventional eDRAM was performance. When reading a bit of data eDRAM by its nature discharges the storage capacitor.  This charge must be restored after a write operation. Thus, while the read cycle time of SRAM in a 65nm process is 1ns, the comparable read cycle time of eDRAM is 2ns. The gain cell reduces this disparity by eliminating the destructive read operation. This results in not only achieving a read performance equivalent to SRAM, it also reduces the active power needed for each read operation.

A 64kb eDRAM array built using the gain cell technology has been implemented in a 65nm test chip and the performance data cited above has been validated.  Now it remains to build a processor system with the gain-cell eDRAM replacing the SRAM cache.

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