2T Bit Cell Memory Architecture
How Does the Technology Work?
An antifuse is the opposite of an eFuse. The circuit is open (high resistance) to begin with and is programmed closed by applying electrical stress that creates a low resistance conductive path. Antifuse NVM has been implemented for many decades using additional processing steps. Kilopass was the first to pioneer antifuse in a standard CMOS process with no additional processing steps.
A hard gate oxide breakdown is used as the one-time programmable non-volatile memory mechanism. The breakdown is achieved by applying a high voltage on the program gate (WLP) shown in the figure above. Before the breakdown, between the gate and the source of the program transistor, it is isolated like a capacitor. After the breakdown, it behaves like a resistor between the gate and the source. The program transistor is isolated from the select transistor (WLR). Both the program and read transistors are implemented using core devices so as the technology scales, the bitcell scales.
Why 2T Bit Cell Architecture?
- Reliability is the same as foundry’s process
- Exclusive use of standard Vt NMOS devices as supplied from the foundry
- Compatibility with CMOS baseline logic process technology
- No additional masks or processing steps required
- Manufacturability for high volume production; proven yield
- No additional overlay tolerance or process control required
- Standard NMOS transistor, not a new transistor
- Follows DFM design rules
- No Additional wafer processing operations
- No wafer bake
- No UV erase
To request more information, please email info@kilopass.com
White Papers
- Integrating High Density Antifuse OTP NVM for Code Storage
- A Comparison of Embedded Non-Volatile Memory Technologies and Their Applications
- Eliminating Embedded Non-
Volatile Memory IP Risks in SOCs - Three Application Segments Require On-Chip OTP
- Profitable SoC Design: Using Logic NVM to Reduce SoC Costs
- Firmware Storage for Signal Processing